XCS05XL Xilinx, XCS05XL Datasheet - Page 8

• Manufacturer Part Number: XCS05XL
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: Xilinx

Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 4: Supported Sources for Spartan/XL Inputs
Table 5: I/O Standards Supported by Spartan-XL FPGAs
Additional Fast Capture Input Latch (Spartan-XL only)
The Spartan-XL IOB has an additional optional latch on the
input. This latch is clocked by the clock used for the output
flip-flop rather than the input clock. Therefore, two different
clocks can be used to clock the two input storage elements.
This additional latch allows the fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent Low Fast Capture latch
followed by a transparent High input latch. Any of the clock
inputs can be inverted before driving the library element,
and the inverter is absorbed into the IOB.
IOB Output Signal Path
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in
8
LVCMOS 3V
Spartan family, V
TTL outputs (V
Signaling
Any device, V
Standard
Any device, V
Any device, V
LVTTL
PCI5V
PCI3V
TTL
CMOS outputs
CMOS outputs
TTL outputs
Source
CC
OH
CC
CC
Not allowed
Not allowed
CC
Clamping
= 3.3V,
Required
= 5V,
= 5V,
3.7V)
= 5V,
VCC
OK
OK
TTL
5V,
Spartan
Inputs
12/24 mA
12/24 mA
12/24 mA
Output
24 mA
12 mA
Drive
CMOS
Unreli-
Data
able
5V,
Table
6.
Spartan-XL
Inputs
CMOS
mode)
(default
3.3V
V
IH MAX
5.5
3.6
5.5
3.6
3.6
www.xilinx.com
1-800-255-7778
50% of V
50% of V
Spartan-XL V
Spartan-XL FPGAs have an optional clamping diode con-
nected from each I/O to V
ringing transients back to the 3.3V supply rail. This clamping
action is required in 3.3V PCI applications. V
a global option affecting all I/O pins.
Spartan-XL devices are fully 5V TTL I/O compatible if V
clamping is not enabled. With V
Spartan-XL devices will begin to clamp input voltages to
one diode voltage drop above V
patibility is maintained but full 5V I/O tolerance is sacrificed.
The user may select either 5V tolerance (default) or 3.3V
PCI compatibility. In both cases negative voltage is clamped
to one diode voltage drop below ground.
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in
Table 6: Output Flip-Flop Functionality
Power-Up
V
Flip-Flop
Legend:
or GSR
IH MIN
2.0
2.0
2.0
Mode
SR
0*
1*
X
Z
CC
CC
CC
Don’t care
Rising edge (clock not inverted).
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Clock
30% of V
30% of V
Table
X
X
X
0
V
Clamping
IL MAX
0.8
0.8
0.8
5.
Enable
Clock
CC
CC
1*
X
0
X
X
CC
DS060 (v1.6) September 19, 2001
. When enabled they clamp
90% of V
90% of V
CC
V
CC
OH MIN
. If enabled, TTL I/O com-
2.4
2.4
2.4
0*
0*
0*
0*
T
1
clamping enabled, the
Product Specification
CC
CC
D
D
X
X
X
X
CC
10% of V
10% of V
V
clamping is
OL MAX
0.4
0.4
0.4
SR
Q
Q
D
Q
Z
CC
CC
CC
R