AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 112
AMD-K6
Manufacturer Part Number
AMD-K6
Description
AMD-K6 Processor
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AMD-K6.pdf
(346 pages)
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AMD-K6
5.19
Summary
Sampled
94
®
Processor Data Sheet
EADS# (External Address Strobe)
Input
System logic asserts EADS # during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of
the address bus by asserting AHOLD or BOFF# or by receiving
HLDA. The processor responds to the sampling of EADS# and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s cache, and HITM#, which
indicates if it is in the modified state.
If AHOLD or BOFF# is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
EADS # two clock edges after AHOLD or BOFF # is sampled
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock edges after the clock edge HLDA is asserted by the
processor.
EADS# is ignored during the following conditions:
One clock edge after the clock edge on which EADS# is
sampled asserted
Two clock edges after the clock edge on which ADS# is
asserted
When the processor is driving the address bus
When the processor asserts HITM#
Preliminary Information
Signal Descriptions
20695H/0—March 1998
Chapter 5
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