AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 114

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
5.21
Summary
Driven
96
®
Processor Data Sheet
FERR# (Floating-Point Error)
Output
The assertion of FERR # indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 189 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR# signal.
The processor ensures that FERR# does not glitch, enabling the
signal to be used as a clocking source for system logic.
The processor asserts FERR # on the instruction boundary of
the next floating-point instruction, MMX instruction, or WAIT
instruction that occurs following the floating-point instruction
that caused the unmasked floating-point exception—that is,
FERR # is not asserted at the time the exception occurs. The
IGNNE# signal does not affect the assertion of FERR#.
FERR# is negated during the following conditions:
FERR# is always driven except in Tri-State Test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 100 for
more details on floating-point exceptions.
Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
Under certain circumstances, following the successful
execution of the floating-point
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
Following the falling transition of RESET
Preliminary Information
Signal Descriptions
instructions FLDCW,
20695H/0—March 1998
Chapter 5