AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 194

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
8.5
176
®
Processor Data Sheet
Cache-Line Fills
For the system logic to flush the cache, the processor must
sample FLUSH# asserted. In this method, the processor writes
back any data cache lines that are in the modified state,
invalidates all lines in the instruction and data caches, and then
executes a flush acknowledge special cycle (See Table 19 on
page 119).
Software can use two different instructions to flush the cache.
Both the WBINVD and INVD instructions cause all cache lines
to be marked invalid. The WBINVD instruction causes all
modified lines to first be written back to memory. The INVD
instruction invalidates all cache lines without writing modified
lines back to memory.
Any area of system memory can be cached. However, the
processor prevents caching of locked operations and TLB reads,
the operating system can prevent caching of certain pages by
setting the PCD and PWT bits in the PDE or PTE, and system
logic can prevent caching of certain bus cycles by negating the
KEN# input signal with the first BRDY# or NA# of a cycle.
When the CPU needs to read memory, the processor drives a
read cycle onto the bus. If the cycle is cacheable the CPU
asserts CACHE#. The system logic also has control of the
cacheability of bus cycles. If it determines the address is
cacheable, system logic asserts the KEN# signal and the
appropriate value of WB/WT#.
One of two events takes place next. If the cycle is not cacheable,
a non-pipelined, single-transfer read takes place. The processor
waits for the system logic to return the data and assert a single
BRDY# (See Figure 45 on page 127). If the cycle is cacheable,
the processor executes a 32-byte burst read cycle. The processor
expects to sample BRDY# asserted a total of four times for a
burst read cycle to take place (See Figure 47 on page 131).
Instruction-cache line fills initiate 32-byte transfers from
memory (one burst cycle) on the bus. Data-cache line fills also
initiate 32-byte transfers on the bus. If the data-cache line being
filled replaces a modified line, the prior contents of the line are
copied to a 32-byte writeback (copyback) buffer in the bus
interface unit while the new line is being read.
Preliminary Information
Cache Organization
20695H/0—March 1998
Chapter 8