AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 265
AMD-K6
Manufacturer Part Number
AMD-K6
Description
AMD-K6 Processor
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AMD-K6.pdf
(346 pages)
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20695H/0—March 1998
Table 50. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Chapter 16
Notes:
Symbol
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
t
t
t
t
t
t
t
t
t
t
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t
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t
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71
74
81
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
HOLD Setup Time
HOLD Hold Time
IGNNE# Setup Time
IGNNE# Hold Time
INIT Setup Time
INIT Hold Time
INTR Setup Time
INTR Hold Time
INV Setup Time
INV Hold Time
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
NMI Setup Time
NMI Hold Time
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
Parameter Description
Signal Switching Characteristics
5.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
4.5 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
5.0 ns
4.5 ns
1.0 ns
1.5 ns
1.0 ns
1.0 ns
1.0 ns
Min
Preliminary Data
Max
Figure
AMD-K6
86
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®
Processor Data Sheet
Comments
Note 1
Note 1
Note 2
Note 2
Note 1
Note 1
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
247
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