AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 188
AMD-K6
Manufacturer Part Number
AMD-K6
Description
AMD-K6 Processor
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AMD-K6.pdf
(346 pages)
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AMD-K6
7.4
170
®
Processor Data Sheet
State of Processor After INIT
Table 26. Register State After RESET (continued)
The recognition of the assertion of INIT causes the processor to
empty its pipelines, to initialize most of its internal state, and to
branch to address FFFF_FFF0h—the same instruction
execution starting point used after RESET. Unlike RESET, the
p r o c e s s o r p re s e rve s t h e c o n t e n t s o f i t s c a c h e s , t h e
floating-point state, the MMX state, MSRs, and the CD and NW
bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
2. EDX contains the AMD-K6 processor signature, where X indicates the processor Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
Power-on Configuration and Initialization
If EAX is non-zero, BIST failed.
Register
WHCR
MCAR
MCTR
TR12
Preliminary Information
DR7
DR6
DR3
DR2
DR1
DR0
CR3
CR4
TSC
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000h
0000_0000h
0000_0400h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
FFFF_0FF0h
State (hex)
20695H/0—March 1998
Chapter 7
Notes
3
3
3
3
3
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