STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet

STPC4EDBC

Manufacturer Part Number

STPC4EDBC

Description

X86 Core PC Compatible Information Appliance System-on-Chip

Manufacturer

STMICROELECTRONICS [STMicroelectronics]

Datasheet

1.STPC4EDBC.pdf (93 pages)

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X86 Core PC Compatible Information Appliance System-on-Chip

DESCRIPTION

The STPC Consumer-II integrates a standard 5th

generation x86 core, a Synchronous DRAM

controller, a graphics subsystem, a video pipeline,

and support logic including PCI, ISA, and IDE

controllers

orientated PC compatible subsystem on a single

device.

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing memory

between the CPU, the graphics and the video.

The STPC Consumer-II is packaged in a 388

Plastic Ball Grid Array (PBGA).

POWERFUL x86 PROCESSOR

64-BIT SDRAM UMA CONTROLLER

VGA & SVGA CRT CONTROLLER

135 MHz RAMDAC

2D GRAPHICS ENGINE

VIDEO INPUT PORT

VIDEO PIPELINE

- UP-SCALER

- VIDEO COLOUR SPACE CONVERTER

- CHROMA & COLOUR KEY SUPPORT

TV OUTPUT

- THREE-LINE FLICKER FILTER

- ITU-R 601/656 SCAN CONVERTER

- NTSC / PAL COMPOSITE, RGB, S-VIDEO

PCI MASTER / SLAVE / ARBITER

ISA MASTER / SLAVE

OPTIONAL 16-BIT LOCAL BUS INTERFACE

EIDE CONTROLLER

I²C INTERFACE

IPC

- DMA CONTROLLER

- INTERRUPT CONTROLLER

- TIMER / COUNTERS

POWER MANAGEMENT UNIT

JTAG IEEE1149.1

provide

single

Release 1.5 - January 29, 2002

consumer

Host

I/F

SDRAM

STPC

CTRL

Core

x86

Pipeline

Figure 0-1. Logic Diagram

Video

SVGA

CRTC

CTR

PCI

m/s

VIP

CONSUMER-II

PBGA388

IPC

Cursor

C Key

K Key

LUT

PMU

ISA

m/s

TVO

JTAG

PCI

m/s

ISA Bus

Local Bus

Encoder

IDE

I/F

PCI Bus

Monitor

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