STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 31

• Manufacturer Part Number: STPC4EDBC
• Description: X86 Core PC Compatible Information Appliance System-on-Chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

3.1.4. CPC STRAP REGISTER 0 CONFIGURATION
HCLK_Strap
Bit Number Sampled
MD[3}
MD[3]
7
Bits 7-3
Bits 2-0
0
0
0
0
0
1
1
MD[2]
6
MD[2]
MD[3:2] & MD[26:24]
0
0
0
0
1
0
1
This register defaults to the values sampled on MD pins after reset
Mnemonic
Rsv
MD[26]
Table 3-1. HCLK Frequency Programming
5
MD[26]
0
0
0
0
0
0
0
Release 1.5 - January 29, 2002
Access = 0022h/0023h
Description
These pins reflect the values sampled on MD[3:2] and
MD[26:24] pins respectively and control the Host clock
frequency synthesizer as shown in
Reserved
MD[25]
4
MD[25]
0
0
1
1
0
1
0
MD[24]
3
MD[24]
0
1
0
1
1
1
1
2
Table 3-1
Rsv
STRAP OPTIONS
1
HCLK Speed
100 MHz
25 MHz
50 MHz
60 MHz
66 MHz
75 MHz
90 MHz
Regoffset = 05Fh
0
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