STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 40

• Manufacturer Part Number: STPC4EDBC
• Description: X86 Core PC Compatible Information Appliance System-on-Chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure
of the SDRAM interface.
Table 4-10. SDRAM Bus AC Timing
For correct operation, the programmable read
clock delay (RDCLK) must be activated for the
CRTC and the delay set to the minimum. This is
done by setting the Latch_CRTC_Data_In bit in
the SDRAM Controller register 0 and clear the
bits[3:0] in register 1.
40/93
Note: These timing are for a load of 50pF.
Toutput
Tsetup
Tdelay
Tcycle
MCLKx
MCLKI
STPC.output
STPC.input
Name
Thigh
Thold
Tlow
4-5,
Table 4-10
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to Outputs Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MD[63:0] setup to MCKLI
MD[63:0] hold from MCKLI
lists the AC characteristics
T
hold
T
delay
Figure 4-5. SDRAM Timing Diagram
Release 1.5 - January 29, 2002
T
output (max)
T
high
The PC133 memory is recommended to reach
100MHz operation.
T
cycle
T
setup
T
T
output (min)
low
3.75
Min
5.2
6.5
6.5
1.3
10
4
4
Typ
-0.9
Max
8.8
8.8
4.0
2.5
1
1
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns