STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 69

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STPC4EDBC

Manufacturer Part Number
STPC4EDBC
Description
X86 Core PC Compatible Information Appliance System-on-Chip
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure
PCICLKI
PCICLKO
6-8. This approach is also recommended
Implementation 1
CY2305
Figure 6-8. PCI clock routing with zero-delay clock buffer
PLL
Release 1.5 - January 29, 2002
Device A
Device B
Device C
Device D
when implementing the delay on PCICLKI
according to the PCI section of the Electrical
Specifications chapter.
PCICLKI
PCICLKO
Implementation 2
CY2305
PLL
DESIGN GUIDELINES
Device A
Device B
Device C
Device D
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