ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 18

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

ENC28J60
3.1.2
The ECON2 register, shown in Register 3-2, is used to
control other main functions of the ENC28J60.
REGISTER 3-2:
DS39662B-page 16
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
AUTOINC
R/W-1
This bit is automatically cleared once it is set.
ECON2 REGISTER
AUTOINC: Automatic Buffer Pointer Increment Enable bit
1 = Automatically increment ERDPT or EWRPT on reading from or writing to EDATA
0 = Do not automatically change ERDPT and EWRPT after the buffer is accessed
PKTDEC: Packet Decrement bit
1 = Decrement the EPKTCNT register by one
0 = Leave EPKTCNT unchanged
PWRSV: Power Save Enable bit
1 = MAC, PHY and control logic are in Low-Power Sleep mode
0 = Normal operation
Reserved: Maintain as ‘0’
VRPS: Voltage Regulator Power Save Enable bit
When PWRSV = 1:
1 = Internal voltage regulator is in Low-Current mode
0 = Internal voltage regulator is in Normal Current mode
When PWRSV = 0:
The bit is ignored; the regulator always outputs as much current as the device requires.
Unimplemented: Read as ‘0’
PKTDEC
R/W-0
ECON2: ETHERNET CONTROL REGISTER 2
(1)
W = Writable bit
‘1’ = Bit is set
PWRSV
R/W-0
R/W-0
Preliminary
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
VRPS
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
U-0
—
U-0
—
bit 0