ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 58

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

ENC28J60
To enable flow control on the ENC28J60 in Full-Duplex
mode, the host controller must set the TXPAUS and
RXPAUS bits in the MACON1 register. Then, at any time
that the receiver buffer is running out of space, the host
controller should turn flow control on by writing the value
02h to the EFLOCON register. The hardware will period-
ically transmit pause frames loaded with the pause timer
value specified in the EPAUS registers. The host
controller can continue to transmit its own packets
without interfering with the flow control hardware.
When space has been made available for more packets
in the receive buffer, the host controller should turn flow
control off by writing the value 03h to the EFLOCON
register. The hardware will send one last pause frame
loaded with a pause timer value of 0000h. When the
pause frame is received by the remote node, it will
resume normal network operations.
REGISTER 10-1:
DS39662B-page 56
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2
bit 1-0
U-0
—
Unimplemented: Read as ‘0’
FULDPXS: Read-Only MAC Full-Duplex Shadow bit
1 = MAC is configured for Full-Duplex mode, FULDPX (MACON3<0>) is set
0 = MAC is configured for Half-Duplex mode, FULDPX (MACON3<0>) is clear
FCEN1:FCEN0: Flow Control Enable bits
When FULDPXS = 1:
11 = Send one pause frame with a ‘0’ timer value and then turn flow control off
10 = Send pause frames periodically
01 = Send one pause frame then turn flow control off
00 = Flow control off
When FULDPXS = 0:
11 = Flow control on
10 = Flow control off
01 = Flow control on
00 = Flow control off
U-0
—
EFLOCON: ETHERNET FLOW CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
When RXPAUS is set in the MACON1 register and a
valid pause frame arrives with a non-zero pause timer
value,
transmissions.
ECON1.TXRTS bit to send a packet, the hardware will
simply wait until the pause timer expires before
attempting to send the packet and subsequently clearing
the TXRTS bit. Normally, the host controller will never
know that a pause frame has been received. However, if
it is desirable to the host controller to know when the
MAC is paused or not, it should set the PASSALL bit in
MACON1 and then manually interpret the pause control
frames which may arrive.
U-0
—
the
FULDPXS
ENC28J60
R-0
If
the
© 2006 Microchip Technology Inc.
x = Bit is unknown
host
will
FCEN1
R/W-0
controller
automatically
FCEN0
R/W-0
sets
inhibit
bit 0
the