ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 73

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

13.0
The ENC28J60 incorporates a dual purpose DMA
controller which can be used to copy data between
locations within the 8-Kbyte memory buffer. It can also
be used to calculate a 16-bit checksum which is
compatible with various industry standard protocols,
including TCP and IP.
When a DMA operation begins, the EDMAST register
pair is copied into an Internal Source Pointer. The DMA
will execute on one byte at a time and then increment
the Internal Source Pointer. However, if a byte is
processed and the Internal Source Pointer is equal to
the Receive Buffer End Pointer, ERXND, the Source
Pointer will not be incremented. Instead, the Internal
Source Pointer will be loaded with the Receive Buffer
Start Pointer, ERXST. In this way, the DMA will follow
the circular FIFO structure of the receive buffer and
received packets can be processed using one opera-
tion. The DMA operation will end when the Internal
Source Pointer matches the EDMAND Pointer.
While any DMA operation is in progress, the DMA
Pointers and the ECON1.CSUMEN bit should not be
modified. The DMA operation can be canceled at any
time by clearing the ECON1.DMAST bit. No registers
will change; however, some memory bytes may already
have been copied if a DMA copy was in progress.
© 2006 Microchip Technology Inc.
Note 1: If the EDMAND Pointer cannot be
2: By design, the DMA module cannot
DIRECT MEMORY ACCESS
CONTROLLER
reached because of the receive buffer
wrapping behavior, the DMA operation
will never end.
be used
(EDMAST = EDMAND). An attempt to
do so will overwrite all memory in the
buffer and may never end.
to
copy
only one
byte
Preliminary
13.1
To copy memory within the buffer:
1.
2.
3.
4.
If a transmit operation is in progress (TXRTS set) while
the DMAST bit is set, the ENC28J60 will wait until the
transmit operation is complete before attempting to do
the DMA copy. This possible delay is required because
the DMA and transmission engine share the same
memory access port.
When the copy is complete, the DMA hardware will
clear the DMAST bit, set the DMAIF bit and generate
an interrupt (if enabled). The Pointers and the
EDMACS registers will not be modified.
After the DMA module has been initialized and has
begun its copy, two main clock cycles will be required
for each byte copied. As a result, if a maximum size
1518-byte packet was copied, the DMA module would
require slightly more than 121.44 s to complete. The
time required to copy a minimum size packet of
64 bytes would be dominated by the time required to
configure the DMA.
Appropriately program the EDMAST, EDMAND
and EDMADST register pairs. The EDMAST
registers should point to the first byte to copy
from, the EDMAND registers should point to the
last byte to copy and the EDMADST registers
should point to the first byte in the destination
range. The destination range will always be
linear, never wrapping at any values except from
8191 to 0 (the 8-Kbyte memory boundary).
Extreme
programming the Start and End Pointers to
prevent a never ending DMA operation which
would overwrite the entire 8-Kbyte buffer.
If an interrupt at the end of the copy process is
desired, set EIE.DMAIE and EIE.INTIE and
clear EIR.DMAIF.
Verify that ECON1.CSUMEN is clear.
Start the DMA copy by setting ECON1.DMAST.
Copying Memory
care
should
ENC28J60
be
DS39662B-page 71
taken
when