ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 28
![no-image](/images/no-image-200.jpg)
ENC28J60-C/ML
Manufacturer Part Number
ENC28J60-C/ML
Description
Stand-Alone Ethernet Controller with SPI Interface
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.ENC28J60-CML.pdf
(96 pages)
- Current page: 28 of 96
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ENC28J60
4.2
The operation of the ENC28J60 depends entirely on
commands given by an external host controller over the
SPI interface. These commands take the form of
instructions, of one or more bytes, which are used to
access the control memory and Ethernet buffer spaces.
At the least, instructions consist of a 3-bit opcode,
TABLE 4-1:
DS39662B-page 26
Read Control Register
(RCR)
Read Buffer Memory
(RBM)
Write Control Register
(WCR)
Write Buffer Memory
(WBM)
Bit Field Set
(BFS)
Bit Field Clear
(BFC)
System Reset Command (Soft Reset)
(SRC)
Legend: a = control register address, d = data payload.
SPI Instruction Set
Name and Mnemonic
Instruction
SPI INSTRUCTION SET FOR THE ENC28J60
0
0
0
0
1
1
1
Opcode
Preliminary
0
0
1
1
0
0
1
0
1
0
1
0
1
1
Byte 0
a
1
a
1
a
a
1
followed by a 5-bit argument that specifies either a
register address or a data constant. Write and bit field
instructions are also followed by one or more bytes of
data.
A total of seven instructions are implemented on the
ENC28J60. Table 4-1 shows the command codes for
all operations.
Argument
a
1
a
1
a
a
1
a
0
a
0
a
a
1
a
1
a
1
a
a
1
a
0
a
0
a
a
1
d
d
d
d
© 2006 Microchip Technology Inc.
Byte 1 and Following
d
d
d
d
d
d
d
d
d
d
d
d
Data
N/A
N/A
N/A
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
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