ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 75

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

14.0
The ENC28J60 may be commanded to power-down
via the SPI interface. When powered down, it will no
longer be able to transmit and receive any packets.
To maximize power savings:
1.
2.
3.
4.
5.
In Sleep mode, all registers and buffer memory will
maintain their states. The ETH registers and buffer
memory will still be accessible by the host controller.
Additionally, the clock driver will continue to operate.
The CLKOUT function will be unaffected (see
Section 2.3 “CLKOUT Pin”).
TABLE 14-1:
© 2006 Microchip Technology Inc.
ESTAT
ECON2
ECON1
Legend: — = unimplemented, read as ‘0’, r = reserved bit. Shaded cells are not used for power-down.
Name
Turn
ECON1.RXEN.
Wait for any in-progress packets to finish being
received by polling ESTAT.RXBUSY. This bit
should be clear before proceeding.
Wait for any current transmissions to end by
confirming ECON1.TXRTS is clear.
Set ECON2.VRPS (if not already set).
Enter Sleep by setting ECON2.PWRSV. All
MAC,
inaccessible as a result. Setting PWRSV also
clears ESTAT.CLKRDY automatically.
POWER-DOWN
off
MII
AUTOINC PKTDEC
TXRST
packet
Bit 7
INT
SUMMARY OF REGISTERS USED WITH POWER-DOWN
and
PHY
reception
BUFER
RXRST
Bit 6
registers
by
PWRSV
DMAST
Bit 5
r
become
clearing
LATECOL
CSUMEN
Preliminary
Bit 4
r
TXRTS
When normal operation is desired, the host controller
must perform a slightly modified procedure:
1.
2.
3.
After leaving Sleep mode, there is a delay of many
milliseconds before a new link is established (assuming
an appropriate link partner is present). The host
controller may wish to wait until the link is established
before attempting to transmit any packets. The link
status
PHSTAT2.LSTAT bit. Alternatively, the link change
interrupt may be used if it is enabled. See
Section 12.1.5
(LINKIF)” for additional details.
VRPS
Bit 3
—
Wake-up by clearing ECON2.PWRSV.
Wait at least 300 s for the PHY to stabilize. To
accomplish the delay, the host controller may
poll ESTAT.CLKRDY and wait for it to become
set.
Restore
ECON1.RXEN.
can
RXBUSY
RXEN
Bit 2
—
receive
be
“Link
determined
TXABRT
BSEL1
Bit 1
—
Change
capability
ENC28J60
CLKRDY
BSEL0
by
Bit 0
DS39662B-page 73
—
Interrupt
by
polling
on page
setting
Values
Reset
13
13
13
Flag
the