ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 44

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

ENC28J60
TABLE 7-2:
DS39662B-page 42
EIE
EIR
ESTAT
ECON1
ETXSTL
ETXSTH
ETXNDL
ETXNDH
MACON1
MACON3
MACON4
MABBIPG
MAIPGL
MAIPGH
MACLCON1
MACLCON2
MAMXFLL
MAMXFLH
Legend:
Register
Name
— = unimplemented, r = reserved bit. Shaded cells are not used.
TX Start Low Byte (ETXST<7:0>)
TX End Low Byte (ETXND<7:0>)
Maximum Frame Length Low Byte (MAMXFL<7:0>)
Maximum Frame Length High Byte (MAMXFL<15:8>)
PADCFG2
TXRST
INTIE
Bit 7
INT
—
—
—
—
—
—
—
—
—
—
SUMMARY OF REGISTERS USED FOR PACKET TRANSMISSION
Back-to-Back Inter-Packet Gap (BBIPG<6:0>)
Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)
Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)
PADCFG1
BUFER
RXRST
DEFER
PKTIE
PKTIF
Bit 6
—
—
—
—
—
Collision Window (COLWIN<5:0>)
PADCFG0
DMAST
DMAIE
DMAIF
BPEN
Bit 5
—
—
—
—
r
TX Start High Byte (ETXST<12:8>)
TX End High Byte (ETXND<12:8>)
TXCRCEN
NOBKOFF
LATECOL
CSUMEN
Preliminary
LINKIE
LINKIF
Bit 4
—
r
Retransmission Maximum (RETMAX<3:0>)
PHDREN
TXPAUS
TXRTS
Bit 3
TXIE
TXIF
—
—
HFRMEN
RXBUSY
RXPAUS
RXEN
Bit 2
—
r
r
FRMLNEN
PASSALL
TXABRT
TXERIE
TXERIF
BSEL1
© 2006 Microchip Technology Inc.
Bit 1
r
MARXEN
CLKRDY
FULDPX
RXERIE
RXERIF
BSEL0
Bit 0
r
on page
Values
Reset
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
14