LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 3

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
SMSC LAN91C965v&3v
3.1
4.1
5.1
5.2
5.3
5.4
5.5
5.6
7.1
7.2
8.1
8.2
8.3
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.13.1
9.13.2
9.13.3
Local Bus vs. PCMCIA vs. 68000 Pin Requirements ________________________________________________ 14
Buffer Symbols _______________________________________________________________________________ 20
Buffer Memory _______________________________________________________________________________ 23
Interrupt Structure____________________________________________________________________________ 30
Reset Logic___________________________________________________________________________________ 31
Power Down Logic States_______________________________________________________________________ 31
LAN91C96 Power Down States __________________________________________________________________ 32
PCMCIA CONFIGURATION REGISTERS DESCRIPTION ________________________________________ 35
I/O Space Access ______________________________________________________________________________ 41
I/O Space Registers Description _________________________________________________________________ 41
Typical Flow of Events for Transmit (Auto Release = 0) _____________________________________________ 67
Typical Flow of Events for Transmit (Auto Release = 1) _____________________________________________ 68
Flow of Events for Receive ______________________________________________________________________ 69
Memory Management Unit _____________________________________________________________________ 79
Arbiter ______________________________________________________________________________________ 79
Bus Interface _________________________________________________________________________________ 80
Wait State Policy ______________________________________________________________________________ 80
Arbitration Considerations _____________________________________________________________________ 81
DMA Block __________________________________________________________________________________ 81
Packet Number FIFOS _________________________________________________________________________ 82
CSMA Block _________________________________________________________________________________ 84
Network Interface _____________________________________________________________________________ 85
10Base-T___________________________________________________________________________________ 86
AUI _______________________________________________________________________________________ 86
Physical Interface ___________________________________________________________________________ 86
Transmit Functions__________________________________________________________________________ 86
General Description _________________________________________________________________________ 6
Overview __________________________________________________________________________________ 7
Pin Configurations_________________________________________________________________________ 10
Description of Pin Functions ________________________________________________________________ 16
Functional Description _____________________________________________________________________ 22
Frame Format in Buffer Memory for Ethernet __________________________________________________ 37
Registers Map in I/O Space __________________________________________________________________ 41
Theory of Operation________________________________________________________________________ 65
Functional Description of the Blocks __________________________________________________________ 79
Manchester Encoding _______________________________________________________________________ 86
Transmit Drivers ___________________________________________________________________________ 87
Jabber Function____________________________________________________________________________ 87
TABLE OF CONTENTS
DATASHEET
Page 3
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Rev. 03-28-07