LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 56

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Note:
Rev. 03-28-07
For software compatibility with future versions, the value read from each FIFO register is intended to be written
into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the
Interrupt Status Register.
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if
TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.
I/O SPACE - BANK2
POINTER REGISTER - The value of this register determines the address to be accessed within the
transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.
The increment is by one for every byte access, and by two for every word access. When RCV is set the
address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is
clear the address refers to the transmit area and uses the packet number at the Packet Number Register.
READ bit - Determines the type of access to follow. If the READ bit is high the operation intended is a
read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high,
generates a pre-fetch into the Data Register for read purposes.
Read-back of the pointer will indicate the value of the address last accessed by the CPU (rather than the
last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without
affecting the process being interrupted.
The Pointer Register should not be loaded until 400ns after the last write operation to the Data Register to
ensure that the Data Register FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data
Register should not be read before 400ns after the pointer was loaded to allow the Data Register FIFO to
fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
ETEN bit - When set enables EARLY Transmit underrun detection. Normal operation when clear.
If TCR bit 14 (ETEN-TYPE) is zero and this bit is set, the Early transmit underrun function will be enabled
as it was implemented in the LAN91C94:
"The Early Transmit function allows the CPU to enqueue the first transmit packet before it is fully loaded in
packet memory. The loading operation proceeds in parallel with the transmission, and in the case that the
transmitter gets ahead of the CPU, the LAN91C94 will prevent the transmission of erroneous data by
forcing an Underrun condition. Underruns will be triggered by starving the transmit DMA if the LAN91C96
detects that the DMA TX address exceeds the pointer address.”
If TCR bit 14 (ETEN-TYPE) is zero and this bit is set, the Early transmit underrun function defined as
follows:
OFFSET
RCV
0
0
6
AUTO
INCR.
0
0
READ
POINTER REGISTER
0
0
DATASHEET
NAME
ETEN
POINTER LOW
0
0
Page 56
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
AutoTx
0
0
READ/WRITE
0
0
TYPE
POINTER HIGH
0
0
SYMBOL
SMSC LAN91C965v&3v
PTR
0
0