LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 54

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Notes:
Rev. 03-28-07
Only command 2 uses N2, N1 and N0.
When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
MMU commands releasing memory (commands 8 and A) should only be issued if the corresponding packet
number has memory allocated to it.
1110
The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET
MMU command, the RESET TX FIFOs does not release any memory.
COMMAND SEQUENCING
A second allocate command (command 2) should not be issued until the present one has completed.
Completion is determined by reading the FAILED bit of the allocation result register or through the
allocation interrupt. A second release command (commands 8 and A) should not be issued if the previous
one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing
command A, the contents of the PNR should not be changed until BUSY goes low. After issuing command
8, command 6 should not be issued until BUSY goes low. BUSY BIT - Readable at bit “0” of the MMU
command register address. When set indicates that MMU is still processing a release command. When
clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the
trailing edge of command.
I/O SPACE - BANK2
AUTO TX START REGISTER - This register specifies the value, in 16 byte multiples of when the transmit
state machine starts a transmit operation when the associated transmit buffer is enqueued into the
transmit FIFO.
The AutoTx bit as well as the ETEN bit must both be set in the pointer register in order for this register to
be utilized. Note: This register must be non-zero for the Auto-Tx function to work. A value of ”0” will disable
this function. The RCV bit in the Pointer register must be zero (0) as well. The RCV bit must be cleared so
that the packet being written and enqueued is being selected by the PNR and not the receive FIFO.
Register Operation: When Early Transmit is enabled via the ETEN bit in the pointer register, the host is
able to enqueue a buffer for transmit operation before all of the transmitted data is copied into the
LAN91C96 dual ported RAM. In the case of the AutoTx bit being cleared, the host must manually start the
transmit operation. When the AutoTx bit is set, the EPH Transmit engine compares the number of bytes
moved into the transmit packet buffer with the value of the Auto TX Start Register to start transmit
operation. This eliminates the requirement for the host to manually start the transmit.
OFFSET
D7
0
1
D6
0
F)
AUTO TX START REGISTER
RESET TX FIFOs - This command will reset both TX FIFOs. The TX FIFO
holding the packet numbers awaiting transmission and the TX Completion FIFO.
This command provides a mechanism for canceling packet transmissions, and
reordering or bypassing the transmit queue.
D5
0
DATASHEET
NAME
D4
0
Page 54
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
D3
0
READ/WRITE
D2
0
TYPE
D1
0
SYMBOL
AUTOTX
SMSC LAN91C965v&3v
D0
0