LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 5
LAN91C96_07
Manufacturer Part Number
LAN91C96_07
Description
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN91C96_07.pdf
(125 pages)
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Figure 12.14 – External ROM Read Access Using Bale ............................................................................................112
Figure 12.15 - EEPROM Read...................................................................................................................................113
Figure 12.16 - EEPROM Write ...................................................................................................................................114
Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) .................................................................................115
Figure 12.18 – External ENDEC Interface – Start of Transmit ...................................................................................115
Figure 12.19 – External ENDEC Interface – Receive Data ........................................................................................116
Figure 12.20 – Differential Output Signal Timing (10BASE-T and AUI) .....................................................................117
Figure 12.21 – Receive Timing – Start of Frame (AUI and 10BASE-T) .....................................................................118
Figure 12.22 – Receive Timing – End of Frame (AUI and 10BASE-T).......................................................................119
Figure 12.23 – Transmit Timing – End of Frame (AUI and 10BASE-T)......................................................................120
Figure 12.24 – Collision Timing (AUI) ........................................................................................................................121
Figure 12.25 – Memory Read Timing.........................................................................................................................121
Figure 12.26 – Input Clock Timing .............................................................................................................................122
Figure 12.27 – Memory Write Timing .........................................................................................................................122
Figure 12.28 - 100 PIN QFP Package........................................................................................................................123
Figure 12.29 - 100 PIN TQFP Package .....................................................................................................................124
LIST OF TABLES
Table 5.1 - LAN91C96 Address Space ........................................................................................................................29
Table 5.2 - Bus Transactions In LOCAL BUS Mode ....................................................................................................29
Table 5.3 - Bus Transactions In PCMCIA Mode...........................................................................................................30
Table 5.4 - Bus Transactions In 68000 Mode................................................................................................................30
Table 5.5 - Interrupt Merging........................................................................................................................................31
Table 5.6 - LOCAL BUS Mode Defined States (Refer To Table 5.7 For Next States To Wake-Up Events).................32
Table 5.7- LOCAL BUS Mode ......................................................................................................................................32
Table 5.8 - PCMCIA Mode (Refer To Table 5.7 For Next States To Wake-Up Events) ...............................................33
Table 5.9 - PCMCIA Mode ...........................................................................................................................................33
Table 7.1 - Transmit Loop ............................................................................................................................................44
SMSC LAN91C965v&3v
Page 5
Rev. 03-28-07
DATASHEET
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