LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 37

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Chapter 6
SMSC LAN91C965v&3v
The frame format in memory is similar to that in the TRANSMIT and RECEIVE areas. The first word is
reserved for the status word, the next word is used to specify the total number of bytes, and that in turn is
followed by the data area. The data area holds the packet itself, and its length is determined by the byte
count. The frame memory format is word oriented.
BYTE COUNT - Divided by two, it defines the total number of words, including the STATUS WORD, the
BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always
appears as even, the ODDFRM bit of the receive status word indicates if the low byte of the last word is
1534 Max
(DECIMAL)
CONTROL BYTE
STATUS WORD
OFFSET
BYTE COUNT
DATA AREA
RAM
0
2
4
Frame Format in Buffer Memory for
Ethernet
bit15
RESERVED
2nd Byte
CONTROL BYTE
Last Byte
Written by CSMA upon transmit
completion (see Status Register)
Written by CPU
Written/modified by CPU
Written by CPU to control
ODD/EVEN data bytes
Figure 6.1 – Data Frame Format
DATASHEET
TRANSMIT PACKET
Page 37
STATUS WORD
DATA AREA
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
BYTE COUNT (always even)
LAST DATA BYTE (if odd)
Written by CSMA upon receive
completion (see RX Frame
Status Word)
Written by CSMA
Written by CSMA
Written by CSMA. Also has
ODD/EVEN bit
RECEIVE PACKET
1st Byte
bit0
Rev. 03-28-07