PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 308

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
19.5.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Start (S) and Stop (P) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
the bus is Idle, with both the Start and Stop bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 19-18:
DS39931D-page 308
SDAx
SCLx
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
Write to the SSPxBUF register initiating
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
2
C bus may be taken when the Stop bit is set, or
MASTER MODE
2
C bus operations based on Start and
2
C port to receive data.
MSSPx BLOCK DIAGRAM (I
SDAx In
Bus Collision
SCLx In
Read
MSb
Write Collision Detect
End of XMIT/RCV
Start bit, Stop bit,
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPxBUF
SSPxSR
Generate
2
C™ MASTER MODE)
LSb
Write
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmitted
• Repeated Start
Clock
Data Bus
Shift
Internal
Note:
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
2
C Master mode, does not allow queueing
 2011 Microchip Technology Inc.
SSPxADD<6:0>
SSPM<3:0>
Generator
Baud
Rate