PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 364

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
22.2.4
Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’
represents the endpoint number). Each register has an
identical complement of control bits.
provides the prototype.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint. Setting this bit enables USB handshak-
ing. Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transac-
tions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
REGISTER 22-4:
DS39931D-page 364
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
USB ENDPOINT CONTROL
Unimplemented: Read as ‘0’
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake is enabled
0 = Endpoint handshake is disabled (typically used for isochronous endpoints)
EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers are allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers are also allowed
EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output is enabled
0 = Endpoint n output is disabled
EPINEN: Endpoint Input Enable bit
1 = Endpoint n input is enabled
0 = Endpoint n input is disabled
EPSTALL: Endpoint Stall Indicator bit
1 = Endpoint n has issued one or more STALL packets
0 = Endpoint n has not issued any STALL packets
U-0
—
UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
(BANKED F26h-F35h)
W = Writable bit
‘1’ = Bit is set
U-0
—
Register 22-4
EPHSHK
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPCONDIS
R/W-0
transactions. For Endpoint 0, this bit should always be
cleared
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or
disable USB OUT transactions from the host. Setting
this bit enables OUT transactions. Similarly, the
EPINEN bit (UEPn<1>) enables or disables USB IN
transactions from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
point pair will be set by the SIE. This bit remains set
until it is cleared through firmware or until the SIE is
reset.
since
EPOUTEN
R/W-0
the
USB
 2011 Microchip Technology Inc.
x = Bit is unknown
EPINEN
R/W-0
specifications
EPSTALL
R/W-0
identify
bit 0