PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 63

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

5.0
The PIC18F46J50 family of devices differentiate
among various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers.
FIGURE 5-1:
 2011 Microchip Technology Inc.
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Deep Sleep Reset
MCLR
DDCORE
Note 1: The V
V
DD
RESET
Deep Sleep Reset
2: The V
Pointer
Stack
(CONFIG3L<2>) Configuration bit. On “F” devices, the V
Sleep mode by DSBOREN (CONFIG3L<2>).
Sleep mode. The V
Configuration Word Mismatch
PWRT
Timer
Brown-out
INTRC
( )_IDLE
V
Time-out
Reset
DD
Detect
WDT
Sleep
DDCORE
DD
Rise
External Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
(1)
monitoring BOR circuit can be enabled or disabled on “LF” devices based on the DSBOREN
RESET Instruction
(WDT)
monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep
POR Pulse
PWRT
F: 5-Bit Ripple Counter
LF: 11-Bit Ripple Counter
DDCORE
Brown-out
Reset
Reset
monitoring BOR circuit has a trip point threshold of V
(2)
(during
PIC18F46J50 FAMILY
For information on WDT Resets, see
“Watchdog Timer
see Section 6.1.4.4 “Stack Full and Underflow
Resets” and for Deep Sleep mode, see
“Deep Sleep
Figure 5-1
on-chip Reset circuit.
5.1
Device Reset events are tracked through the RCON
register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in
Registers”.
DD
monitoring BOR circuit is only enabled during Deep
(Register
RCON Register
provides a simplified block diagram of the
Mode”.
5-1). The lower five bits of the register
(WDT)”. For Stack Reset events,
BOR
Section 5.7 “Reset State of
S
R
(Parameter D005).
Q
DS39931D-page 63
Chip_Reset
Section 27.2
Section 4.6