MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 258

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MC68HC912D60A

Manufacturer Part Number
MC68HC912D60A
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Enhanced Capture Timer
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
MCCNTH/L — Modulus Down-Counter Count Register
Technical Data
258
RESET:
RESET:
$00B6
$00B7
$00B2
$00B3
$00B4
$00B5
BIt 15
BIT 7
Bit 7
BIT 7
BIt 7
BIt 7
Bit 7
Bit 7
1
0
14
6
6
1
6
6
6
6
6
0
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see
Read: any time
Write: any time
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pulse
13
5
5
1
5
5
5
5
5
0
Accumulators).
Go to: www.freescale.com
Enhanced Capture Timer
12
4
4
1
4
4
4
4
4
0
11
3
3
1
3
3
3
3
3
0
10
2
2
1
2
2
2
2
2
0
1
9
1
1
MC68HC912D60A — Rev 3.0
1
1
1
1
1
0
BIT 0
Bit 8
Bit 0
1
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
$00B2–$00B5
$00B6, $00B7
MOTOROLA
MCCNTH
MCCNTL
PA3H
PA2H
PA1H
PA0H

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