HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 10

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HD6417606

Manufacturer Part Number
HD6417606
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 6 Interrupt Controller (INTC)................................................................. 81
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Section 7 Bus State Controller (BSC) ............................................................. 107
7.1
7.2
7.3
7.4
7.5
Rev. 4.00 Sep. 13, 2007 Page x of xxvi
Features................................................................................................................................ 81
Input/Output Pins................................................................................................................. 83
Register Descriptions........................................................................................................... 83
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources.................................................................................................................. 98
6.4.1
6.4.2
6.4.3
6.4.4
Interrupt Exception Handling Vector Table....................................................................... 100
Interrupt Operation ............................................................................................................ 102
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 104
Features.............................................................................................................................. 107
Input/Output Pins............................................................................................................... 110
Area Overview................................................................................................................... 111
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions......................................................................................................... 115
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
Operation ........................................................................................................................... 143
7.5.1
7.5.2
7.5.3
Interrupt Control Register 0 (ICR0)........................................................................ 84
IRQ Control Register (IRQCR) .............................................................................. 84
IRQ Status Register (IRQSR) ................................................................................. 88
Interrupt Priority Registers A to E (IPRA to IPRE)................................................ 94
External Interrupts .................................................................................................. 98
On-Chip Peripheral Module Interrupts ................................................................... 99
User Break Interrupt ............................................................................................... 99
H-UDI Interrupt .................................................................................................... 100
Interrupt Sequence ................................................................................................ 102
Stack after Interrupt Exception Handling ............................................................. 104
Area Division........................................................................................................ 111
Shadow Area......................................................................................................... 111
Address Map......................................................................................................... 112
Area 0 Memory Type and Memory Bus Width .................................................... 114
Data Alignment..................................................................................................... 114
Common Control Register (CMNCR) .................................................................. 116
CSn Space Bus Control Register (CSnBCR) (n = 0, 3, 4, 5B, 6B)....................... 117
CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) .................... 122
SDRAM Control Register (SDCR)....................................................................... 138
Refresh Timer Control/Status Register (RTCSR)................................................. 139
Refresh Timer Counter (RTCNT)......................................................................... 141
Refresh Time Constant Register (RTCOR) .......................................................... 142
Endian/Access Size and Data Alignment.............................................................. 143
Normal Space Interface ........................................................................................ 148
Access Wait Control ............................................................................................. 152

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