HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 350

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Host Interface (HIF)
When the external DMAC is specified to detect the falling edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 0. After writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is
generated at the HIFDREQ pin.
When the external DMAC is specified to detect the rising edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after
writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ
pin.
Rev. 4.00 Sep. 13, 2007 Page 324 of 502
REJ09B0239-0400
HIFDREQ
HIFDREQ
HIFDREQ
DTRG bit
DTRG bit
DTRG bit
DPOL bit
DPOL bit
DPOL bit
HIFCS
HIFRS
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
Figure 13.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)
Figure 13.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)
Figure 13.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
Negated when HIFCS = HIFRS = low level.
Latency is t
After assert, negated when
t
PCYC
After assert, negated when
t
PCYC
(peripheral clock cycle) × 32 cyc have elapsed.
PCYC
(peripheral clock cycle) × 32 cyc have elapsed.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
(peripheral clock cycle) × 3 cyc or less.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.