HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 214

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the
I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is driven high in a word-size
I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8
bits and data is accessed twice in units of eight bits in the I/O bus cycle to be executed.
The IOIS16 signal is sampled at the falling edge of the CKIO signal in the Tpci0, Tpci0w, and
Tpci1 cycles when bits TED3 to TED0 are specified as 1.5 cycles or more, and is reflected in the
CE2 signal 1.5 cycles after the CKIO sampling point. Bits TED3 to TED0 must be specified
appropriately to satisfy the setup time of the PC card from ICIORD and ICIOWR to CEn.
Figure 7.36 shows the dynamic bus sizing basic timing.
Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the
IOIS16 signal must be fixed low.
Tpci1
Tpci1w
Tpci1w
Tpci1w
Tpci2
CKIO
A25 to A0
CExx
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
Figure 7.34 Basic Timing for PCMCIA I/O Card Interface
Rev. 4.00 Sep. 13, 2007 Page 188 of 502
REJ09B0239-0400