HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 414

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 User Break Controller (UBC)
decremented by 1. A break is issued when the break condition is satisfied after BETR becomes
H'0001.
16.2.11 Branch Source Register (BRSR)
BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source
instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on
reset. Other bits are not initialized by a power-on reset. The four BRSR registers have a queue
structure and a stored register is shifted at every branch.
Rev. 4.00 Sep. 13, 2007 Page 388 of 502
REJ09B0239-0400
Bit
15 to 12
11 to 0
Bit
31
30 to 28
27 to 0
Bit Name
SVF
—
BSA27 to
BSA0
Bit Name
—
BET11 to
BET0
Initial
Value
0
All 0
Undefined
Initial
Value
All 0
All 0
R/W
R
R/W
R/W
R
R
R
Description
These bits are always read as 0. The write value should
always be 0.
Reserved
Number of Execution Times
Description
BRSR Valid Flag
Indicates whether or not the branch source address is
stored. When a branch is made, this flag is set to 1.
This flag is cleared to 0 by one of the following
conditions: when this flag is read from this register,
when PC trace is enabled, and when a power-on reset
is generated.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid
Reserved
These bits are always read as 0. The write value should
always be 0.
Branch Source Address
Store bits 27 to 0 of the branch source address.