HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 422
HD6417606
Manufacturer Part Number
HD6417606
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Section 16 User Break Controller (UBC)
• Register specifications
Break Condition Specified for L Bus Data Access Cycle:
• Register specifications
Rev. 4.00 Sep. 13, 2007 Page 396 of 502
REJ09B0239-0400
Channel A
Channel B
On channel A, a user break occurs before an instruction of address H'00000500 is executed.
On channel B, a user break occurs after the instruction of address H'00001000 are executed
four times and before the fifth time.
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400
Specified conditions: Channel A/channel B independent mode
Channel A
Channel B
A user break occurs after an instruction of addresses H'00008000 to H'00008FFE is executed
or before an instruction of addresses H'00008010 to H'00008016 is executed.
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
Address: H'00000500, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The ASID check is not included.
Address: H'00001000, Address mask: H'00000000
Data: H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
Address: H'00008404, Address mask: H'00000FFF
Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
Address: H'00008010, Address mask: H'00000006
Data: H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
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