HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 148

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
7.4.3
CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register
varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0)
specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the
target area. Specify CSnBCR first, then specify CSnWCR.
Normal Space, Byte-Selection SRAM:
• CS0WCR
Rev. 4.00 Sep. 13, 2007 Page 122 of 502
REJ09B0239-0400
Bit
31 to 13
12
11
CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B)
Bit Name

SW1
SW0
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WEn (BEn) assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles