HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 178

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
7.5.3
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have the same access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 7.9.
When the WM bit in CSnWCR is cleared to 0, the external wait signal (WAIT) is also sampled.
The WAIT pin sampling is shown in figure 7.9. In this example, two wait cycles are inserted as
software wait. The WAIT signal is sampled at the falling edge of the CKIO signal in the cycle
immediately before the T2 cycle (T1 or Tw cycle).
Rev. 4.00 Sep. 13, 2007 Page 152 of 502
REJ09B0239-0400
Access Wait Control
Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)
Read
Write
A25 to A0
D15 to D0
D15 to D0
WEn (BEn)
RD/WR
CKIO
CSn
RD
BS
T1
Tw
T2