HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 179

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

7.5.4
The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation
to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 7.10 shows an example. A Th cycle and a Tf cycle are
added before and after a normal cycle, respectively. In these cycles, RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
Figure 7.9 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT)
Extension of Chip Select (CSn) Assertion Period
Read
Write
A25 to A0
D15 to D0
WEn (BEn)
D15 to D0
RD/WR
CKIO
WAIT
CSn
RD
BS
T1
Tw
Tw
Rev. 4.00 Sep. 13, 2007 Page 153 of 502
Wait cycles inserted
Twx
Section 7 Bus State Controller (BSC)
by WAIT signal
T2
REJ09B0239-0400