HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 104

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

3.2.5
The MMU control register (MMUCR) makes the MMU settings. Any program that modifies
MMUCR should reside in the P1 or P2 area.
Rev. 4.00, 03/04, page 58 of 660
Bit
31 to 9
8
7, 6
5, 4
3
2
1
0
Bit Name
SV
RC
TF
IX
AT
MMU Control Register (MMUCR)
Initial Value R/W Description
All 0
All 0
All 0
0
0
0
0
R
R/W Single virtual memory mode
R
R/W Random counter
R
R/W TLB flush
R/W Index mode
R/W Address translation
Reserved
These bits are always read as 0. The write value should
always be 0.
0: multiple virtual memory mode
1: single virtual memory mode
Reserved
These bits are always read as 0. The write value should
always be 0.
A 2-bit random counter, automatically updated by
hardware according to the following rules in the event of
an MMU exception. When a TLB miss exception occurs,
all TLB entry ways corresponding to the virtual address at
which the exception occurred are checked, and if all ways
are valid, 1 is added to RO; if there is one or more invalid
ways, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU
exception other than a TLB miss exception, the way
which caused the exception is set in RC.
Reserved
This bit is always read as 0. The write value should
always be 0.
When 1 is set, all valid bits of TLB are cleared to 0 (flush).
This bit is always reads as 0.
When 0, VPN bits 16 to 12 are used as the TLB index
number. When 1, the value obtained by EX-ORing ASID
bits 4 to 0 in PTEH and VPN bits 16 to 12 are used as the
TLB index number.
Enables (valid) or disables (invalid) the MMU.
0: MMU disabled
1: MMU enabled