HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 67

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The data format in memory is shown in figure 2.5.
2.3
2.3.1
Data Length: The instruction set is implemented with fixed-length 16-bit wide instructions
executed in a pipelined sequence with single-cycle execution for most instructions. All operations
are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32-
bit longword units, with byte or word units sign-extended into 32-bit longwords. Literals are sign-
extended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and zero-extended in
logical operations (TST, AND, OR, and XOR instructions).
Load/Store Architecture: The load-store architecture is used, so basic operations are executed by
the registers. Operations requiring memory access are executed in registers following register
loading, except for bit-manipulation operations such as logical AND functions, which are executed
directly in memory.
Delayed Branching: Unconditional branching is implemented as delayed branch operations.
Pipeline disruptions due to branching are minimized by the execution of the instruction following
the delayed branch instruction prior to branching. Conditional branch instructions are of two
kinds, delayed and normal.
BRA
ADD
Address A + 4
Address A + 8
Address A
Instruction Features
Execution Environment
TRGET
R1, R0
Address A
31
Byte0
Address A + 1
Word0
23
Big-endian mode
Byte1
;ADD is executed prior to branching to TRGET
Figure 2.5 Data Format in Memory
Longword
Address A + 2
15
Byte2
Word1
Address A + 3
7
Byte3
0
Address A + 11
31
Byte3
Word1
Address A + 10
Little-endian mode
23
Byte2
Longword
Address A + 9
15
Byte1
Rev. 4.00, 03/04, page 21 of 660
Word0
7
Address A + 8
Byte0
0
Address A + 8
Address A + 4
Address A