HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 167

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.4
The INTC has the following registers. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
6.4.1
The interrupt priority level setting registers A to E (IPRA to IPRE) are 16-bit read/write registers
that set priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are
initialized to H'0000 at power-on reset, manual reset, or in hardware standby mode, but is not
initialized in standby mode.
Table 6.6 lists the relationship between the interrupt sources and the IPRA to IPRE bits.
Table 6.6
Note:
As shown in table 6.6, four sets of on-chip peripheral module, IRQ interrupts are assigned to each
register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values
from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is
priority level 15 (the highest level). A reset initializes IPRA to IPRE to H'0000.
H'0 should be set into bits corresponding to an unused interrupt.
Register
IPRA
IPRB
IPRC
IPRD
IPRE
Interrupt control register 0 (ICR0)
Interrupt control register 1 (ICR1)
Interrupt priority level setting register A (IPRA)
Interrupt priority level setting register B (IPRB)
Interrupt priority level setting register C (IPRC)
Interrupt priority level setting register D (IPRD)
Interrupt priority level setting register E (IPRE)
Interrupt request register 0 (IRR0)
Interrupt request register 1 (IRR1)
Interrupt request register 2 (IRR2)
* These bits are always read as 0. The write value should be 0.
Register Description
Interrupt Priority Registers A to E (IPRA to IPRE)
Interrupt Request Sources and IPRA to IPRE
Bits 15 to 12
TMU0
WDT
IRQ3
Reserved*
DMAC
Bits 11 to 8
TMU1
REF
IRQ2
Reserved*
Reserved*
Bits 7 to 4
TMU2
SCI0
IRQ1
IRQ5
SCIF
Rev. 4.00, 03/04, page 121 of 660
Bits 3 to 0
RTC
Reserved*
IRQ0
IRQ4
ADC