HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 11

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
3.3.2 TLB Indexing
3.5.2 TLB Protection
Violation Exception
3.6.3 Usage Examples
6.4.4 Interrupt Request
Register 0 (IRR0)
8.3 Area Overview
Figure 8.2 Corresponding to
Logical Address Space and
Physical Address Space
8.4.6 PCMCIA Control
Register (PCR)
8.5.2 Description of Areas
Page
61
71
78
126
163
185
197
Revision (See Manual for Details)
Description added
The TLB uses a 4-way set associative scheme, so entries must be
selected by index. VPN bits 16 to 12 and ASID bits in PTEH 4 to 0
are used as the index number regardless of the page size.
Description added
Software (TLB Protection Violation Handler) Operations: Software
resolves the TLB protection violation and issues the RTE (return from
exception handler) instruction to terminate the handler and return to
the instruction stream. Note that the RTE instruction should be
issued after the two instructions following the LDTLB instruction.
Description deleted
Invalidating Specific Entries: Specific TLB entries can be invalidated
by writing 0 to the entry's V bit. R0 specifies the write data and R1
specifies the address.
Bit 5 R/W amended
(Before) R
Note amended
Note: For logical address spaces P0 and P3, when the memory
Bit table of bits 11, 7, 6 amended
Description added
cycles using the A0W2 to A0W0 bits of WCR2. In addition, any
number of waits can be inserted in each bus cycle by means of the
external wait pin (WAIT). When the burst function is used, the bus
cycle pitch of the burst cycle is determined within a range of 2 to 10
according to the number of waits.
Bit*
13, 12
11
7
6
The number of bus cycles is selected between 0 and 10 wait
management unit (MMU) is on, it can optionally generate a
physical address for the logical address. It can be applied when
the MMU is off and when the MMU is on and each physical
address for the logical address is equal except for upper three
bits. See table 8.2, Physical Address Space Map, for
information on converting logical addresses into user-defined
physical addresses.
Bit Name
—
A5TED2
A5TED1
A5TED0
(After) R/W
Initial Value
All 0
0
0
0
Rev. 4.00, 03/04, page xi of xlvi
R/W
R
R/W
R/W
R/W