HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 110

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

3.3.4
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or non-
cacheable area of memory. The PR field specifies the access rights for the page in privileged and
user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB
protection violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 3.1.
Table 3.1
Rev. 4.00, 03/04, page 64 of 660
D bit
C bit
PR bit
Page Management Information
0
1
0
1
00
01
10
11
Access States Designated by D, C, and PR Bits
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
Permitted
Permitted
Permitted
Permitted
Privileged Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
Permitted
TLB protection
violation exception
Permitted
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
Permitted
Permitted
User Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
TLB protection
violation exception
Permitted