HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 131

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next
instruction when a delayed conditional branch instruction is true.
4.1.4
Table 4.2 lists the exception codes written to bits 11 to 0 of the EXPEVT register for reset or
general exceptions or the INTEVT and INTEVT2 registers for general interrupt requests to
identify each specific exception event. An additional exception register, the TRAPA (TRA)
register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction).
Table 4.2
Exception Type
Reset
General exception events
Exception Codes
Exception Codes
Exception Event
Power-on reset
Manual reset
H-UDI reset
TLB miss/invalid exception (load)
TLB miss/invalid exception (store)
Initial page write exception
TLB protection exception (load)
TLB protection exception (store)
CPU Address error (load)
CPU Address error (store)
Unconditional trap (TRAPA instruction)
Reserved instruction code exception
Illegal slot instruction exception
User breakpoint trap
DMA address error
Rev. 4.00, 03/04, page 85 of 660
Exception Code
H'000
H'020
H'000
H'040
H'060
H'080
H'0A0
H'0C0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'5C0