PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 124

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 26
Clock Source
Receive Data
(1.544 Mbit/s on RL1/RL2,
RDIP/RDIN or ROID)
Receive Data
in case of LOS
DCO-R
The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.
In digital bipolar line interface mode the clock and data recovery requires HDB3 coded
signals with 50% duty cycle.
5.1.6
The B8ZS line code or the AMI (ZCS, zero code suppression) coding is provided for the
data received from the ternary or the dual rail interface. All code violations that do not
correspond to zero substitution rules are detected. If a bit error causes a code violation
that leads to a valid substitution pattern, this code violation is not detected and the
substitution pattern is replaced by the corresponding zero pattern. The detected errors
increment the 16-bit code violation counter. In case of the optical interface a selection
between the NRZ code and the CMI Code (1T2B) with B8ZS or AMI postprocessing is
provided. If CMI code is selected the receive route clock is recovered from the data
stream. The CMI decoder does not correct any errors. In case of NRZ coding data is
latched with the falling edge RCLKI.
When using the optical interface with NRZ coding, the decoder is bypassed and no code
violations are detected.
Additionally, the receive line interface contains the alarm detection for Alarm Indication
Signal AIS (Blue Alarm) and the loss-of-signal LOS (Red Alarm).
User’s Manual
Hardware Description
Receive Line Coding (T1/J1)
RCLK Output Selection (T1/J1)
RCLK Frequency
1.544 MHz
constant high
1.544 MHz
(generated by DCO-R,
synchronized on SYNC)
1.544 MHz
2.048 MHz
6.176 MHz
8.192 MHz
124
Functional Description T1/J1
CMR1.
DCS
1
CMR1.
RS1/0
00
01
10
10
10
11
11
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
SIC2.
SSC2
1
1
0
1
0
®
56