PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 44

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 4
Pin or
Ball No.
60 (B8)
61 (A9)
62 (A8)
63 (B7)
User’s Manual
Hardware Description
Name
XPA
XPB
XBC
XPD
Pin Definitions - System Interface (cont’d)
Pin
Type
I
I
O
O
Buffer
Type
PU
PU
Function
Transmit Signaling Data (XSIG)
PC(1:4).XPC(3:0) = 0010
Input for transmit signaling data received from
the signaling highway. Optionally,
(SIC3.TTRF = 1), sampling of XSIG data is
controlled by the active high XSIGM marker.
At higher data rates sampling of data is
defined by bits SIC2.SICS(2:0).
Transmit Clock (TCLK)
PC(1:4).XPC(3:0) = 0011
A 2.048/8.192-MHz (E1) or 1.544/6.176-MHz
(T1/J1) clock has to be sourced by the system
if the internally generated transmit clock
(generated by DCO-X) shall not be used.
Optionally this input is used as a
synchronization clock for the DCO-X circuitry
with a frequency of 2.048 (E1) or 1.544 MHz
(T1/J1).
Transmit Multiframe Begin (XMFB)
PC(1:4).XPC(3:0) = 0100
XMFB marks the beginning of every
transmitted multiframe on XDI. The signal is
active high for one 2.048 (E1) or 1.544 MHz
(T1/J1) period.
Transmit Signaling Marker (XSIGM)
PC(1:4).XPC(3:0) = 0101
E1:
T1/J1: Marks the transmit time slots on XDI of
44
Marks the transmit time slots on XDI of
every frame which are defined by
register TTR(1:4).
every frame which are defined by
register TTR(1:4) (if not CAS-BR is
used). When using the CAS-BR
signaling scheme the robbed bit of
each channel in every sixth frame is
marked.
B
B
B
B
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56