PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 221

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

8.3.8
The FALC
as follows (HDLC channel 1 only):
•
•
User’s Manual
Hardware Description
Sampling of DL-bits is done on a multiframe basis and stored in the registers
RDL(3:1). A receive multiframe begin interrupt is provided to read the received data
DL-bits. The contents of registers XDL(3:1) is subsequently sent out on the transmit
multiframe basis if it is enabled via FMR1.EDL. A transmit multiframe begin interrupt
requests for writing new information to the DL-bit registers.
If enabled via CCR1.EDLX/EITS = 10, the DL-bit information is stored in the receive
FIFO of the signaling controller. The DL-bits stored in the XFIFO are inserted into the
outgoing data stream. If CCR1.EDLX is cleared, a HDLC frame or a transparent
frame can be sent or received via the RFIFO/XFIFO.
®
Data Link Access in ESF/F72 Format (T1/J1)
56 supports the DL-channel protocol using the ESF or F72 (SLC96) format
221
Signaling Controller Operating Modes
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56