HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 103

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
11) MIN (
12) The
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
14) 0
15) 85 °C
16) x4 & x8 (1k page size)
17) The
18) x16 (2k page size), not on 256 Mbit component
19) The maximum limit for the
20) Minimum
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
Data Sheet
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
recognized as low.
WR refers to the WR parameter stored in the MR.
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
this value can be greater than the minimum specification limits for
no longer driving (
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
between 85 °C and 95 °C.
but system performance (bus turnaround) degrades accordingly.
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing
mode” (MR, A12 =”1”) a slow power-down exit timing
T
t
t
CASE
HZ
RRD
t
CL
,
,
T
t
timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
t
RPST
CASE
t
CH
WTR
85 °C
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
and
is two clocks when operating the DDR2-SDRAM at frequencies
95 °C
t
t
HZ
LZ
,
,
t
t
RPRE
RPST
t
WPST
), or begins driving (
parameters are referenced to a specific voltage level, which specify when the device output is
parameter is not a device limit. The device operates with a greater value for this parameter,
V
REF
V
stabilizes. During the period before
TT
t
. See Chapter 8 for the reference load for timing measurements.
LZ
,
t
RPRE
t
XARDS
).
103
t
HZ
has to be satisfied.
and
t
t
LZ
CL
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
transitions occur in the same access time windows
and
t
XARD
t
CH
).
can be used. In “low active power-down
V
t
200
CK
REF
refers to the application clock period.
stabilizes, CKE = 0.2 x
512-Mbit DDR2 SDRAM
z.
Electrical Characteristics
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01
V
DDQ
is