HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 47

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

3.16
Posted CAS operation is supported to make command
and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM
allows a Read or Write command to be issued
immediately after the bank activate command (or any
time during the RAS to CAS delay time,
The command is held for the time of the Additive
Latency (AL) before it is issued inside the device. The
Read Latency (RL) is the sum of AL and the CAS
Figure 19
Activate to Read delay <
Figure 20
Activate to Read delay <
Data Sheet
CK, CK
CMD
DQ
DQS,
DQS
CK, CK
CMD
DQ
Posted CAS
DQS,
DQS
Activate to Read Timing Example: Read followed by a write to the same bank
Read to Write Timing Example: Read followed by a write to the same bank
Activate
Bank A
0
Activate
Bank A
0
Bank A
Read
t
1
t
RCD.MIN
RCD.MIN
Bank A
Read
1
tRCD
AL = 2
tRCD
AL = 2
2
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
2
RL = AL + CL = 5
RL = AL + CL = 5
3
3
t
RCD
4
4
CL = 3
period).
CL = 3
5
Bank A
5
Write
47
6
latency (CL). Therefore if a user chooses to issue a
Read/Write command before the
greater than 0 must be written into the EMR(1). The
Write Latency (WL) is always defined as RL - 1 (Read
Latency -1) where Read Latency is defined as the sum
of Additive Latency plus CAS latency (RL=AL+CL). If a
user chooses to issue a Read command after the
t
RL = AL + CL.
Dout0 Dout1Dout2 Dout3 Dout4 Dout5 Dout6 Dout7
RCD.MIN
6
Dout0Dout1 Dout2Dout3
WL = RL -1 = 4
Bank A
Write
7
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
7
period, the Read Latency is also defined as
WL = RL -1 = 4
8
8
9
Din0
9
Din1
10
512-Mbit DDR2 SDRAM
10
Din2
Din3
Functional Description
Din0
11
09112003-SDM9-IQ3P
11
PostCAS
Din1
PostCAS3
t
Rev. 1.3, 2005-01
RCD.MIN
Din2
12
Din3
, then AL