HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 17

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 4
Ball#/Pin#
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
Data Strobe 4 8 organisations
B7
A8
Data Strobe 8 organisations
B3
A2
Data Strobe 16 organization
B7
A8
F7
E8
Data Mask 4 8 organizations
Data Sheet
Pin Configuration of DDR SDRAM
Name
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DQS
RDQS
RDQS
UDQS
UDQS
LDQS
LDQS
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for 16 components
Data Strobe
Note: Output with read data, input with write data. Edge aligned
Read Data Strobe
Read Data Strobe
Data Strobe Upper Byte
Data Strobe Lower Byte
with read data, centered with write data. For the 16, LDQS
corresponds to the data on DQ[7:0]; UDQS corresponds to
the data on DQ[15:8]. The datastrobes DQS, LDQS, UDQS
may be used in single ended mode or paired with the
optional complementary signals DQS, LDQS, UDQS and
RDQS to provide differential pair signaling to the system
during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals
17
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
Pin Configuration and Block Diagrams
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01