ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 123

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

2486M–AVR–12/03
When configured as a Master, the SPI interface has no automatic control of the SS line.
This must be handled by user software before communication can start. When this is
done, writing a byte to the SPI Data Register starts the SPI clock generator, and the
hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener-
ator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit
(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue
to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high
the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for
later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated
as long as the SS pin is driven high. In this state, software may update the contents of
the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE,
in the SPCR Register is set, an interrupt is requested. The Slave may continue to place
new data to be sent into SPDR before reading the incoming data. The last incoming byte
will be kept in the Buffer Register for later use.
Figure 58. SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive
direction. This means that bytes to be transmitted cannot be written to the SPI Data
Register before the entire shift cycle is completed. When receiving data, however, a
received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To
ensure correct sampling of the clock signal, the frequency of the SPI clock should never
exceed f
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is
overridden according to Table 47. For more details on automatic port overrides, refer to
“Alternate Port Functions” on page 54.
Table 47. SPI Pin Overrides
Note:
CLOCK GENERATOR
MOSI
MISO
SCK
Pin
SS
MSB
8 BIT SHIFT REGISTER
1. See “Port B Pins Alternate Functions” on page 56 for a detailed description of how to
osc
/4.
define the direction of the user defined SPI pins.
SPI
Direction, Master SPI
User Defined
Input
User Defined
User Defined
MASTER
LSB
(1)
V
MISO
MOSI
SCK
SS
CC
MISO
MOSI
SCK
SS
Direction, Slave SPI
Input
User Defined
Input
Input
MSB
8 BIT SHIFT REGISTER
ATmega8(L)
SLAVE
SHIFT
ENABLE
LSB
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