ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 197
![no-image](/images/no-image-200.jpg)
ATMEGA8L
Manufacturer Part Number
ATMEGA8L
Description
8-bit AVR with 8K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-6AU
Manufacturer:
ATMEL
Quantity:
675
Company:
Part Number:
ATMEGA8L-8AI
Manufacturer:
MICROCHIP
Quantity:
1 292
Company:
Part Number:
ATMEGA8L-8AU
Manufacturer:
ATMEL
Quantity:
4 590
Company:
Part Number:
ATMEGA8L-8AU
Manufacturer:
Atmel
Quantity:
7 500
Company:
Part Number:
ATMEGA8L-8AU
Manufacturer:
ATMEL
Quantity:
591
Part Number:
ATMEGA8L-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Changing Channel or
Reference Selection
2486M–AVR–12/03
Figure 94. ADC Timing Diagram, Free Running Conversion
Table 73. ADC Conversion Time
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user
is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
If both ADFR and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is
based on the old or the new settings. ADMUX can be safely updated in the following
ways:
1. When ADFR or ADEN is cleared.
2. During conversion, minimum one ADC clock cycle after the trigger event.
3. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next
ADC conversion.
Condition
Extended conversion
Normal conversions, single ended
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
Complete
One Conversion
11
from Start of Conversion)
Sample & Hold (Cycles
12
13
13.5
Next Conversion
1
1.5
MSB of Result
LSB of Result
2
MUX and REFS
Update
3
Sample &Hold
4
ATmega8(L)
Conversion Time
(Cycles)
25
13
197