ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 42
ATMEGA8L
Manufacturer Part Number
ATMEGA8L
Description
8-bit AVR with 8K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
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42
ATmega8(L)
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-
ing procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 17.
Table 17. Watchdog Timer Prescale Select
The following code example shows one assembly and one C function for turning off the
WDT. The example assumes that interrupts are controlled (for example, by disabling
interrupts globally) so that no interrupts will occur during execution of these functions.
WDP2
0
0
0
0
1
1
1
1
written to WDE even though it is set to one before the disable operation starts.
Watchdog.
WDP1
0
0
1
1
0
0
1
1
WDP0
0
1
0
1
0
1
0
1
1,024K (1,048,576)
2,048K (2,097,152)
Oscillator Cycles
Number of WDT
128K (131,072)
256K (262,144)
512K (524,288)
16K (16,384)
32K (32,768)
64K (65,536)
Typical Time-out
at V
17.1 ms
34.3 ms
68.5 ms
0.14 s
0.27 s
0.55 s
CC
1.1 s
2.2 s
= 3.0V
Typical Time-out
at V
16.3 ms
32.5 ms
2486M–AVR–12/03
65 ms
0.13 s
0.26 s
0.52 s
CC
1.0 s
2.1 s
= 5.0V