ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 33

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Standby Mode
Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Notes:
Minimizing Power
Consumption
Analog-to-Digital Converter
(ADC)
Analog Comparator
2486M–AVR–12/03
Sleep
Mode
Idle
ADC Noise
Reduction
Power
Down
Power
Save
Standby
1. External Crystal or resonator selected as clock source.
2. If AS
3. Only level interrupt INT1 and INT0.
(1)
clk
CPU
2
bit in ASSR is set.
Active Clock Domains
clk
FLASH
clk
X
IO
asynchronous timer should be considered undefined after wake-up in Power-save mode
if AS2 is 0.
This sleep mode basically halts all clocks except clk
chronous modules, including Timer/Counter 2 if clocked asynchronously.
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in 6 clock cycles.
clk
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possi-
ble, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog-to-Digital Con-
verter” on page 193 for details on ADC operation.
When entering Idle mode, the Analog Comparator should be disabled if not used. When
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-
erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 190 for details on how to configure the Analog Comparator.
X
X
ADC
clk
X
X
X
(2)
ASY
Source Enabled
Main Clock
X
X
X
Oscillators
Timer Osc.
Enabled
X
X
X
(2)
(2)
(2)
INT1
INT0
X
X
X
X
X
(3)
(3)
(3)
(3)
Address
Match
ASY
TWI
X
X
X
X
X
, allowing operation only of asyn-
Wake-up Sources
Timer
X
X
X
2
(2)
ATmega8(L)
EEPROM
Ready
SPM/
X
X
ADC
X
X
Other
I/O
X
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