LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 148
LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
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Internal Memory
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
148
Reset
Reset
Type
Type
Bit/Field
31:2
1
0
RO
RO
31
15
0
0
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
RO
RO
30
14
0
0
reserved
PMISC
AMISC
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
RO
RO
Type
27
11
0
0
RO
RO
RO
26
10
0
0
Reset
0
0
0
RO
RO
25
0
9
0
reserved
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 146) is also
cleared when the PMISC bit is cleared.
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
June 04, 2007
R/W1C
PMISC
RO
17
0
1
0
AMISC
R/W1C
RO
16
0
0
0
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